1. Field of the Invention
The present invention relates to integrated circuit devices, particularly integrated circuit memory devices, having output terminals, and to circuitry for driving the output terminals to reduce the time needed to drive output signals on such output terminals.
2. Description of Related Art
Integrated circuits have output terminals, typically referred to as output pads, on which signals are driven for access by external circuitry. The output pads typically have significant capacitance. For this reason output driver circuitry is included that uses large transistors to drive the output pads, or that consumes a significant amount of time in driving in the output pads to the desired signal level. As integrated circuits become more complex, and operate at higher speeds, the area and speed trade-off involved in the output drivers becomes more critical.
For integrated circuit memory devices, the read access time is becoming a critical parameter. The read access time is measured from the beginning of a read cycle until the time that data is available on the output pads for use by the external circuitry.
One factor in read access time depends on the speed of operation of the output drivers. So output drivers are designed with relatively high current circuits to achieve high speed switching. However, high speed switching is prone to noise problems. So pre-driver circuits which drive the output drivers have been designed to reduce noise. However, reducing noise typically involves controlling the rise and fall times of the control signals, which limits the speed of operation. Basically, for high speed switching, a fast current change is needed in the pre-driver circuit. However, noise produced is increased with the rate of change of the current. So contradictory design goals are presented, which require a tradeoff between noise levels and speed.
Background concerning technology that has been developed to address the problems of noise in output drivers can be found in U.S. Pat. No. 5,021,684 entitled PROCESS, SUPPLY, TEMPERATURE COMPENSATING CMOS OUTPUT BUFFER; and U.S. Pat. No. 4,823,029 entitled NOISE CONTROLLED OUTPUT BUFFER.
It is desirable to provide for fast switching of output drivers with reduced noise, suitable for use in large scale integrated circuit memory devices.
The present invention arises from the recognition that output drivers do not generate current when the pull up and pull down circuits are producing control signals which are below the turn on thresholds. Accordingly, no noise is translated to the output of the device in this period of time. Accordingly, an initial drive interval is provided by the present invention in which the pull up and pull down control signals are driven with higher current so that the corresponding signal changes at a higher rate of speed before it reaches the turn on thresholds. Near the turn on thresholds, the rate of change of the pull up and pull down control signals is controlled to minimize noise during the transition and thereafter. A significant speed increase can be achieved with little or no impact on the noise levels generated in the output driver.
Thus, the present invention provides a method for producing a pull up signal and a pull down signal for an output driver responsive to the pull up signal and the pull down signal to produce an output signal at a data output having a high-level when the pull up signal is asserted beyond a pull up threshold, and having a low-level when the pull down signal is asserted beyond a pull down threshold. The method comprises causing a transition of the pull up signal from a starting level of the pull up signal to near the pull up threshold at a first rate of change, and a driving the pull up signal to an ending level beyond the pull up threshold at a second rate of change which is slower than the first-rate change. In a similar fashion, the method includes causing a transition of the pull down signal from a starting level of the pull down signal to near the pull down threshold at a third rate of change, and driving the pull down signal to an ending level beyond the pull down threshold at a fourth rate of change which is slower than the third rate of change.
According to another aspect of the invention, an output circuit for an integrated circuit is provided. The output circuit includes a driver to supply an output signal to an output in response to a control signal. The driver causes a transition in the output signal when the control signal reaches a threshold level. A pre-driver generates the control signal, and includes a first circuit which causes a transition of the control signal from a starting level to near the threshold level at a first rate of change, and a second circuit which drives the control signal to an ending level at a second rate of change which is slower than the first rate of change.
In one embodiment, the second circuit includes a current path having a resistance limiting the rate of change of current driving the transition of the control signal. In this embodiment, the first circuit includes a current path bypassing the resistance while the control signal has a level between the starting level and the threshold level.
In yet another embodiment, the first circuit comprises a component having a capacitance, and a circuit for pre-setting a charge on the capacitance prior to the transition of the control signal. In this embodiment, the capacitance provides charge for accelerating the rate of change of current driving the transition of the control signal as the control signal transitions from the starting level to near the threshold level.
According to a further aspect of the invention, an integrated circuit memory device is provided having a data output. The device comprises a memory array and read circuitry coupled to the memory array to read data in the array and supply a data signal indicating the read data. An output driver is provided which is responsive to a pull up signal and a pull down signal to produce an output signal at the data output. The driver provides a high-level output signal when the pull up signal is asserted beyond a pull up threshold, and provides a low-level output signal when the pull down signal is asserted beyond a pull down threshold. In a one embodiment, when the pull up signal and the pull down signal have a particular combination of levels, then a high impedance is presented to the data output. A pre-driver is coupled to the read circuitry which generates the pull up signal and the pull down signal. The pre-driver includes a first circuit which causes a transition of the pull up signal from a starting level of the pull up signal to near the pull up threshold at a first rate of change, and a second circuit which drives the pull up signal to an ending level beyond the pull up threshold at a second rate of change which is slower than the first rate of change. A third circuit is included in the pre-driver which causes a transition of the pull down signal from a starting level of the pull down signal to near the pull down threshold at a third rate of change, and a fourth circuit which drives the pull down signal to an ending level beyond a pull down threshold at a fourth rate of change which is slower than the third rate of change.
Accordingly, the present invention provides for implementation of high-speed integrated circuit memory devices and other integrated circuits with low noise output drivers. The time interval before current is being driven by the output drivers on such devices is utilized for fast driving of the control signals. When the control signals near or reach the threshold at which current begins to be driven by the output drivers then a lower noise, controlled phase of the control signal transition is implemented.
Other aspects and advantages of the present invention can be seen on review of the figures, the detailed description, and the claims which follow.